Static random access memory(SRAM)is widely used in cache,network equipment and various high-performance systems because of its high-speed reading and writing ability and data stability.Compared with dynamic random access memory(DRAM),SRAM does not need frequent refresh,and uses bistable circuit to latch data internally,but this also makes its cell structure relatively complicated.
 

 

According to the working mode,SRAM can be divided into asynchronous SRAM and synchronous SRAM(SSRAM).The read-write operation of asynchronous SRAM is independent of clock signal,and all data input and output are directly triggered by the change of address line,so the control timing is flexible.Synchronous SRAM binds all access actions to the clock signal,whether it is address,data input or other control signals,which are started synchronously on the rising or falling edge of the clock.This synchronization mechanism enables the system to manage the access timing more accurately,and also makes synchronous SRAM generally superior to asynchronous SRAM in throughput,making it the first choice in scenarios with high bandwidth requirements.
 

 

The speed advantage of synchronous SRAM is not only reflected in clock synchronization,but also the design of its underlying circuit.Each storage bit of synchronous SRAM is usually composed of six metal-oxide-semiconductor field-effect transistor(MOSFET),in which four transistors form two cross-coupled inverters,forming a bistable structure to stably represent a"0"or"1"state;The other two are used as access tubes to control the gating of memory cells during reading and writing.This symmetrical circuit topology makes SRAM need almost no extra charge induction process when reading data,so the access delay is much lower than that of DRAM.In order to compress pins and internal traces,DRAM generally uses the way of multiplexing row address and column address to transmit address information in time-sharing,while synchronous SRAM can receive all address bits at one time,further shortening the access cycle.Synchronous SRAM combines this feature with clock edge latch,which can work stably at frequencies above hundreds of MHz in high-speed systems.